VHDL implementation of the RRISC CPU

A small CPU with a radically reduced instruction set. Hand-crafted. Implemented in VHDL, for use in an FPGA.

Download as .zip Download as .tar.gz View on GitHub

It’s executing its first instruction!!!

lda # $CA    ; load register A with immediate value 0xCA

The instruction lda # $CA does the following:

The image below shows the CPU going out of reset and then executing its first instruction, the instruction above, in 8 clock cycles.

The thin red vertical line to the right in the image is placed at ca. 90 nanoseconds, right after the execute phase of the instruction. In the last, blue line of the diagram you can see cpureg_a (register A) receiving the value CA at the end of execute.

If you look carefully, you can see that value travel from ram_out via debug_inr2 (instruction register 2 containing the operand, the value CA in our case) to register A.


Here is what’s going on in the core of the CPU:

^ toc

< What’s unique about the RRISC CPU

> RRISC Assembly - introduction