VHDL implementation of the RRISC CPU

A small CPU with a radically reduced instruction set. Hand-crafted. Implemented in VHDL, for use in an FPGA.

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At Christmas 2020, I decided to hack on my RRISC CPU. Read all about it here.

In a hurry? See it executing a single instruction here, a complete program here, and in physical form here.

  1. Background and why I built the RRISC CPU
  2. Radical RISC from the early nineties
  3. What’s unique about the RRISC CPU
  4. It’s executing its first instruction
  5. RRISC Assembly - introduction
  6. RRISC Assembler - writing programs
  7. It runs the whole test program
  8. We have an ALU!
  9. Playing with the ALU
  10. Open source, text-based VHDL design: vim, tmux, ghdl, gtkwave
  11. The FPGA
  12. NEW Becoming real: The CPU in action on an FPGA board

This is a work in progess. More info on the minimalistic RRISC CPU will follow as soon as I get to it.

Here is a block diagram of the CPU with periphery of the demo implementation to get you started:


The code is organized as follows: