VHDL implementation of the RRISC CPU

A small CPU with a radically reduced instruction set. Hand-crafted. Implemented in VHDL, for use in an FPGA.

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It’s executing the whole test program!!!

The test program:

What we expect after running this:

As you can see below, both registers contain the value $CA and the program counter falling back to $0009 after reaching $000B.

The red vertical line marks the time of the first jump.


Zooming in to the first jump:


Et voila! The CPU works as expected :-)

^ toc

< RRISC Assembler - writing programs

> We have an ALU