VHDL implementation of the RRISC CPU

A small CPU with a radically reduced instruction set. Hand-crafted. Implemented in VHDL, for use in an FPGA.

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Radical RISC from the early nineties

Let’s walk down memory lane. Here are a few design documents of the original RRISC CPU:

cpu1

cpu2

Microcode image

image

image

Screenshot 2020-12-29 at 07 04 55

Screenshot 2020-12-29 at 07 05 31

Screenshot 2020-12-29 at 06 59 56

Screenshot 2020-12-29 at 07 05 15

load

store

fetch


^ toc

< Background and why I built the RRISC CPU

> What’s unique about the RRISC CPU